1. Field of the Invention
The present invention relates to a data processor with a plurality of general registers, for processing data stored in those general resisters.
2. Description of the Background Art
As an example, we will now describe a conventional data processor including 16 general registers and handling an add instruction with three operands. FIG. 13 illustrates a format of an instruction written in the machine language (a language which a computer can understand) for a data processor. The instruction is 16 bits long in which a bit group a4 designates an operation code and each of bit groups a1 to a3 designates an operand field.
Each bit group a1, a2, a3 of the instruction in the machine language needs four bits to designate an address of a general resister. Thus, a bit group a4 of the remaining four bits is assigned to the operation code.
Next, part of the conventional data processor is shown in FIG. 14. Operand-field storage regions 31, 32, and 33 store the bit groups a1, a2, and a3, respectively. A register group 51 consists of 16 general resistors R0 to R15 to which addresses #R0 to #R15 are assigned, respectively. An example of the instructions executed by this data processor is shown in Table 1.
In Table 1, xe2x80x9cADD/#R2, #R1, #R0xe2x80x9d forms an instruction INa, where xe2x80x9c/xe2x80x9d is a delimiter between the operation code and the operands; ADD is an operation code of a conventional add instruction, corresponding to the bit group a4 in FIG. 13; and #R2, #R1, and #R0 correspond to the bit groups a3, a2, and a1, respectively. At the time of execution of the instruction INa, selectors 52a and 52b read out data from the general registers R0 and R1 corresponding to the bit groups a1 and a2, respectively, in the register group 51. Since the operation code is ADD, an arithmetic circuit 53 adds data obtained by the selector 52a and data obtained by the selector 52b. Then, a selector 54 writes the output of the arithmetic circuit 53 into the general register R2 corresponding to the bit group a3 in the register group 51.
In this fashion, the bit groups a1 and a2 designate storage sources of the data to be processed on the instruction INa and thus called xe2x80x9csource operand,xe2x80x9d while the bit group a3 designates a storage destination of the data to processed on the instruction INa and thus called xe2x80x9cdestination operandxe2x80x9d. In the conventional technique, one instruction has included all the source operands and the destination operand required to carry out one instruction.
In the above example, the bit group a4 is a group of 4 bits, so the data processor can handle only 16 kinds of operation codes. To increase the number of operation codes to be handled by the processor more than 16, the number of bits of the instruction INa has to be increased. Thus, a 32-bit instruction has usually been adopted in the conventional technique. In this way, the increase in the number of operation codes to be handled by the processor results in the increase in the number of bits of the instruction INa.
A first aspect of the present invention is directed to a data processor comprising: a decoding portion receiving an instruction of a program in order, extracting at least one of first operand fields from predetermined bits of the instruction, and decoding an operation code, using the remaining bits; an operand-field storage portion including a first operand-field storage portion storing the first operand field received from the decoding portion, and a second operand-field storage portion storing a second operand field obtained on the basis of the first operand field; and a data processing portion with a plurality of registers, receiving the first operand field and the second operand field from the operand-field storage portion and processing data in registers designated by the first operand field and the second operand field out of the plurality of registers.
According to a second aspect of the present invention, the data processor of the first aspect further comprises: a control circuit detecting the completion of execution of the instruction. When the control circuit detects the completion of execution of the instruction, the operand-field storage portion transfers at least one of the first operand fields from the first operand-field storage portion to the second operand-field storage portion, as the second operand field.
According to a third aspect of the present invention, the data processor of the first aspect further comprises: a data calculation portion receiving at least one of the first operand fields from the decoding portion, calculating the second operand field from the first operand field, and storing the second operand field into the second operand-field storage portion.
According to a fourth aspect of the present invention, the data processor of the second aspect further comprises: a data holding portion saving data stored in the operand-field storage portion when an interruption occurs, and at the end of the interruption, returning the data to the operand-field storage portion.
According to a fifth aspect of the present invention, in the data processor of the first aspect, the decoding portion increases the number of the first operand fields with the instruction of a first kind, as compared with the instruction of a second kind. The data processor further comprises: a selector deciding whether to output the second operand field in the second operand-field storage portion to the processing portion or not depending on the second kind and the first kind of the instruction, respectively.
According to a sixth aspect of the present invention, in the data processor of the fifth aspect, the operation code includes a mode bit indicating whether the instruction is of the first kind or of the second kind.
In the data processor of the first aspect, part of the operand fields required to carry out the instruction is stored in the second operand-field storage portion. This avoids the necessity of including part of the operand fields in the instruction and increases the number of bits of the operation code in the instruction, thereby increasing the number of instructions that the data processor can handle.
In the data processor of the second aspect, when the execution of the instruction is completed, the first operand field can be set as the second operand field.
In the data processor of the third aspect, the data calculation portion can calculate the second operand field from the first operand field.
In the data processor of the fourth aspect, the contents in the operand-field storage portion remain unchanged before and after an interruption. This makes it possible to obtain a processing result originally intended.
In the data processor of the fifth aspect, an instruction using the second operand field in the second operand-field storage portion and an instruction including all operand fields required to carry out the instruction can be mixed in a single program.
In the data processor of the sixth aspect, the first kind and the second kind can be switched on an instruction basis.
Thus, an object of the present invention is to provide a data processor capable of increasing the number of operation codes it can handle, without increasing the number of bits of the instruction.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.